Semiconductor memory device

Static information storage and retrieval – Systems using particular element – Flip-flop

Reexamination Certificate

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C365S072000, C365S174000, C365S189090

Reexamination Certificate

active

07639525

ABSTRACT:
A semiconductor memory device for reducing the power consumption of an entire low power consumption SRAM LSI circuit employing scaled-down transistors and of increasing the stability of read and write operations on the memory cells by reducing the subthreshold leakage current and the leakage current flowing from the drain electrode to the substrate electrode is provided. The semiconductor memory device also prevents an increase in the number of transistors in a memory cell and thereby preventing an increase in the cell area, and ensures stable operation of an SRAM memory cell made up of SOI or FD-SOI transistors having a BOX layer by controlling the potentials of the wells under the BOX layers of the drive transistors.

REFERENCES:
patent: 5986924 (1999-11-01), Yamada
patent: 6643173 (2003-11-01), Takemura
patent: 6898111 (2005-05-01), Yamauchi
patent: 2003/0223276 (2003-12-01), Yamaoka et al.
patent: 2006/0157738 (2006-07-01), Kawanaka
patent: 2007/0029607 (2007-02-01), Kouznetzov
patent: 2008/0055967 (2008-03-01), Houston et al.
patent: 11-039879 (1999-02-01), None
patent: 2003-86713 (2003-03-01), None
patent: 2003-151277 (2003-05-01), None

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