Semiconductor memory device

Static information storage and retrieval – Read/write circuit – Differential sensing

Reexamination Certificate

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C365S149000

Reexamination Certificate

active

07626879

ABSTRACT:
This disclosure concerns a memory comprising memory cells including floating bodies, logic data being stored in the memory cells; word lines connected to gates of the memory cells; bit lines connected to the memory cells; and sense amplifiers connected to the bit lines, and applying a first voltage to the bit lines when first logic data is written to the memory cells connected to the bit lines, wherein the sense amplifiers apply a second voltage to the memory cells having stored therein the first logic data during a refresh operation in which at least second logic data stored in the memory cells is recovered, the second logic data is opposite in logic to the first logic data, and the second voltage is lower in absolute value than the first voltage and equal to or higher in absolute value than a potential of sources of the memory cells.

REFERENCES:
patent: 7139216 (2006-11-01), Higashi et al.
patent: 7277341 (2007-10-01), Fujita et al.
patent: 7301838 (2007-11-01), Waller et al.
patent: 7539041 (2009-05-01), Kim et al.
patent: 2007/0127289 (2007-06-01), Lee
patent: 2005-251256 (2005-09-01), None
patent: 2005-302077 (2005-10-01), None
patent: 2005-302234 (2005-10-01), None
patent: 2007-73680 (2007-03-01), None

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