Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

1999-01-29

2000-07-11

Fears, Terrell W.

Static information storage and retrieval

Addressing

Sync/clocking

36523008, G11C 700

Patent

active

060882913

DESCRIPTION:

BRIEF SUMMARY
FIELD OF THE INVENTION

The present invention generally relates to semiconductor devices, and particularly relates to a semiconductor memory device which operates in synchronism with a clock signal.


BACKGROUND OF THE INVENTION

As processing speed of CPUs is enhanced, semiconductor memory devices such as a DRAM (dynamic random access memory) are required to have an increased data-transfer speed by using an increased signal frequency for input/output of data signals. SDRAMs (synchronous dynamic random access memory) are devised to meet this demand, and operate in synchronism with an input clock signal to achieve a high-operation speed.
FIG. 1 is a circuit diagram showing a portion of a DRAM with regard to peripherals of memory cells. The circuit of FIG. 1 includes a capacitor 501, NMOS transistors 502 through 512, a PMOS transistor 513, PMOS transistors 521 and 522, and NMOS transistors 523 and 524. The PMOS transistors 521 and 522 and the NMOS transistors 523 and 524 together form a sense amplifier 520.
The capacitor 501 serving as a memory cell stores 1-bit information. When a sub-word-line selecting signal SW is activated, the NMOS transistor 502 serving as a cell gate opens, thereby transferring data of the capacitor 501 to a bit-line BL. When this happens, a bit-line-transfer signal BLT1 is at a HIGH level, so that the NMOS transistors 503 and 504 are turned on. A bit-line-transfer signal BLT0, on the other hand, is at a LOW level, so that the NMOS transistors 505 and 506 are turned off. As a result, the data on the bit-lines BL and /BL is stored in the sense amplifier 520 via the NMOS transistors 503 and 504. The sense amplifier 520 operates when the transistors 513 and 512 are turned on via activation of sense-amplifier-activation signals SA1 and SA2, and amplifies the data of the bit-lines BL and /BL. The amplified data on the bit-lines BL and /BL is then sent to data bus DB and /DB via the NMOS transistors 510 and 511 serving as column gates when a column-line selecting signal CL is selectively activated.
In the case of data-write operations, data on the data bus DB and /DB is stored in the capacitor 501 through operation steps reversed in order with reference to the case of data-read operations.
FIG. 2 is timing charts for explaining data-read operations of the DRAM.
As shown in FIG. 2, when data-read operations are conducted, commands are input to the DRAM in an order of a precharge command (PRE) for precharging the bit-lines BL and /BL to a predetermined voltage level, a /RAS command (R) for a row-access operation, and a /CAS command (C) for a column-access operation.
With reference to FIG. 1 and FIG. 2, timing control will be described below with regard to data-read operations.
Upon input of the /RAS command, the bit-line-transfer signal BLT0 becomes LOW (BLT1 is HIGH), so that the bit-lines BL and /BL are connected to the sense amplifier 520. At the same time, a precharge signal PR of FIG. 1 is changed to LOW to end the reset conditions of the bit-lines BL and /BL. Further, a main-word-line selecting signal MW is changed to HIGH, and so is the sub-word-line selecting signal SW, thereby selecting a particular word line. This turns on the NMOS transistor 502, so that the data of the capacitor 501 is read to the bit-line BL. As shown in FIG. 2, the data appears on the bit-line BL at a timing when the main-word-line selecting signal MW and the sub-word-line selecting signal SW become HIGH.
In order to drive the sense amplifier 520, then, sense-amplifier driving signals SA1 and SA2 become active, thereby turning on the NMOS transistor 512 and the PMOS transistor 513. As shown in FIG. 2, activation of the sense amplifier 520 results in an increase in the amplitude of data signals on the bit-lines BL and /BL.
When the amplitude of data signals is stepped up, the column-line selecting signal CL becomes HIGH in response to the /CAS command so as to select a particular column. The NMOS transistors 510 and 511 (column gates) of the selected column are turned on, so that the data is released to the data

REFERENCES:
patent: 4376989 (1983-03-01), Takemae
patent: 5706244 (1998-01-01), Shimizu

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