Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2007-08-28

2009-08-11

Auduong, Gene N. (Department: 2827)

Static information storage and retrieval

Read/write circuit

Testing

C365S185090, C365S233500

Reexamination Certificate

active

07573765

ABSTRACT:
A semiconductor memory device100is proposed including an internal address generation circuit3, a first internal address control signal generation part4, a second internal address control signal generation part11, and an internal address control signal selection circuit10having an OR gate transistor12. The internal address generation circuit3generates an internal address signal based on input address data. The first internal address control signal generation part4generates a first internal address control signal and having a function which fixes the first internal address control signal at a predetermined level with the elapse of a fixed period of time. The second internal address control signal generation part11generates a second internal address control signal corresponding to an input of a predetermined command. The OR gate transistor12transmits either the first internal address control signal or the second internal address control signal to the internal address generation circuit3.

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patent: 2004/0246337 (2004-12-01), Hasegawa et al.
patent: 2004-294224 (2004-10-01), None

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