Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2006-06-02

2008-12-30

Zarabian, Amir (Department: 2827)

Static information storage and retrieval

Systems using particular element

Flip-flop

C156S205000, C156S230000

Reexamination Certificate

active

07471545

ABSTRACT:
Source contacts of driver transistors are short-circuited through the use of an internal metal line within a memory cell. This metal line is isolated from memory cells in an adjacent column and extends in a zigzag form in a direction of the columns of memory cells. Individual lines for transmitting the source voltage of driver transistors can be provided for each column, and the source voltage of driver transistors can be adjusted also in units of memory cell columns in the structure of single port memory cell.

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Technical Report of the Institute of Electronics, Information and Communication Engineers of Japan, vol. 104, No. 66, “Development of Dual Port SRAM for SoC Using 90 nm Technology achieving Increase in Integration and Reduction in Power,” May 20, 2004, Nii et al.
ISSCC2004, Digest of Technical Papers “A 90 nm Dual-Port SRAM with 2.04 μm28T-Thin Cell Using Dynamically-Controlled Column Bias Scheme,” Feb. 18, 2004, Nii et al.
Nii, et al., “Development of Dual Port SRAM for SoC Using 90 nm Technology achieving Increase in Integration and Reduction in Power,” Technical Report of the Institute of Electronics, May 20, 2004, vol. 104, No. 66, Information and Communication Engineers of Japan.
Nii, et al., “A 90 nm Dual-Port SRAM with 2.04 μm28T-Thin Cell Using Dynamically-Controlled Column Bias Scheme,” Digest of Technical Papers, Feb. 18, 2004, ISCC2004.

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