Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2005-10-06

2008-11-11

Jackson, Jerome (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Thin active physical layer which is

Tunneling through region of reduced conductivity

C257S039000, C257S030000, C257S037000

Reexamination Certificate

active

07449713

ABSTRACT:
A semiconductor memory device includes a semiconductor substrate, a semiconductor layer, a source/drain layer, first and second insulating films, and first and second gate electrodes. The semiconductor layer of one conductivity type is formed on a principal surface of the semiconductor substrate. The source/drain layer is formed on the principal surface with being in contact with one end of the semiconductor layer, and has a conductivity type opposite to the one conductivity type. The first insulating film is formed on one side surface of the semiconductor layer. The second insulating film is formed on another side surface of the semiconductor layer. The first gate electrode is formed on the one side surface via the first insulating film. The second gate electrode is formed on the other side surface of the semiconductor layer via the second insulating film, and is opposed to the first gate electrode.

REFERENCES:
patent: 5665979 (1997-09-01), Takahashi et al.
patent: 5828079 (1998-10-01), Mizuno et al.
patent: 2003-209247 (2003-07-01), None
International Technology Roadmap for Semiconductors 2003 Edition, p. 205.
Kuo et al., “A Capacitorless Double Gate DRAM Technology for Sub-100-nm-Embedded and Stand-Alone Memory Applications,” IEEE Transactions on Electron Devices (Dec. 2003), 50:2408-16.
Ohsawa et al., “Memory Design Using a One-Transistor Gain Cell on SOI,” IEEE Journal of Solid-State Circuits (Nov. 2002), 37:1510-1522.

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