Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Bus or line termination
Reexamination Certificate
2006-06-26
2008-11-11
Tran, Anh Q (Department: 2819)
Electronic digital logic circuitry
Signal sensitivity or transmission integrity
Bus or line termination
C326S032000, C326S034000
Reexamination Certificate
active
07449914
ABSTRACT:
A semiconductor memory device includes a code channel for outputting a plurality of code signals based on a code control signal inputted from an external source; a termination resistor decoder for decoding a chip selection signal, an on die termination (ODT) control signal and the plurality of code signals and outputting a plurality of selection signals based on decoded signals; and an ODT block for providing an output data pad with impedance of a termination resistor which is selected in response to the plurality of selection signals.
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patent: 7019555 (2006-03-01), Lee
patent: 7138823 (2006-11-01), Janzen et al.
patent: 2005/0225353 (2005-10-01), Kwon
patent: 2005/0231230 (2005-10-01), Na et al.
patent: 2004-310981 (2004-11-01), None
patent: 2005-228458 (2005-08-01), None
patent: 2003-0090955 (2003-12-01), None
Kim Kyung-Hoon
Kim Yong-Ki
Blakely & Sokoloff, Taylor & Zafman
Hynix / Semiconductor Inc.
Tran Anh Q
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