Error detection/correction and fault detection/recovery – Pulse or data error handling – Error count or rate
Reexamination Certificate
2005-04-11
2008-12-16
Chaudry, M. Mujtaba K. (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Error count or rate
C714S718000, C714S710000
Reexamination Certificate
active
07467337
ABSTRACT:
Disclosed is a semiconductor memory device capable of arbitrarily setting an upper limit of the number of error corrections during a test operation. The semiconductor memory device has a counter, a register, and a comparison circuit. The counter counts the number of error corrections. The register, when an upper limit setting signal is externally inputted to change the upper limit of the number of error corrections, changes the upper limit. The comparison circuit compares the number of error corrections with the changed upper limit.
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Eto Satoshi
Kawabata Kuninori
Kikutake Akira
Nakamura Toshikazu
Onishi Yasuhiro
Arent & Fox LLP
Chaudry M. Mujtaba K.
Fujitsu Limited
Nguyen Steve
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