Semiconductor memory device

Static information storage and retrieval – Systems using particular element – Flip-flop

Reexamination Certificate

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C365S185260, C365S185070

Reexamination Certificate

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07417890

ABSTRACT:
A semiconductor memory device is disclosed, which includes a first SRAM cell which includes cross-connected first and second inverters having first and second nodes, a first transistor connected between a first bit line and the first node and having a gate connected to a first write word line, a second transistor connected between a second bit line and the second node and having a gate connected to the first write word line, a third transistor having a gate connected to the second node, a fourth transistor connected between the first bit line and the third transistor and having a gate connected to a read word line, and a second SRAM cell which includes fifth-eighth transistors corresponding to the first-fourth transistors and has substantially the same configuration as the first SRAM, wherein the drains of the fourth and eighth transistors are connected to the first and second bit lines, respectively.

REFERENCES:
patent: 2004/0114422 (2004-06-01), Yabe
patent: 2005/0201144 (2005-09-01), Kang et al.
patent: 2002-74965 (2002-03-01), None

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