Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2006-02-03

2008-01-08

Phung, Anh (Department: 2824)

Static information storage and retrieval

Read/write circuit

Including level shift or pull-up circuit

C365S094000

Reexamination Certificate

active

07317643

ABSTRACT:
Disclosed herein is a semiconductor memory device which prevents the voltage of a select bit line from being reduced due to the action of coupling capacitance between the select bit line and a non-select bit line and reduces current consumption in the non-select bit line. The semiconductor memory device includes a memory cell array, a plurality of word lines, a plurality of bit lines, a data line, a plurality of selector circuits, at least one precharge circuit, and at least one pull-down circuit. The selector circuits switch electrical connections and isolations between the respective bit lines and the data line. The precharge circuit precharges the select bit line to a predetermined voltage level which is different from a voltage level of a first voltage line. The pull-down circuit pulls the select bit line down to the voltage level of the first voltage line.

REFERENCES:
patent: 5303194 (1994-04-01), Suzuki
patent: 5528534 (1996-06-01), Shoji
patent: 2000-90685 (2000-03-01), None

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