Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2008-01-22

2008-01-22

Ho, Hoai V. (Department: 2827)

Static information storage and retrieval

Read/write circuit

Signals

C365S201000, C365S203000, C365S230030, C365S230060

Reexamination Certificate

active

11260200

ABSTRACT:
An equalizing circuit connects a pair of bit lines to each other in response to the activation of an equalizing control signal and connects the pair of bit lines to a precharge voltage line. An equalizing control circuit deactivates the equalizing control signal in response to the activation of a first timing signal. A word line driving circuit activates one of word lines in response to the activation of a second timing signal. A first signal generating circuit of a timing control circuit generates the first timing signal. A second signal generating circuit of the timing control circuit activates the second timing signal after the deactivation of the equalizing control signal accompanying the activation of the first timing signal. A delay control circuit of the second signal generating circuit delays an activation timing of the second timing signal in a test mode from that in a normal mode.

REFERENCES:
patent: 5365482 (1994-11-01), Nakayama
patent: 6341089 (2002-01-01), Sawada et al.
patent: 6343038 (2002-01-01), Makino et al.
patent: 6925022 (2005-08-01), Arimoto et al.
patent: 2004/0165452 (2004-08-01), Nakano
patent: 2001-76498 (2001-03-01), None
patent: 2002-15598 (2002-01-01), None

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