Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2007-10-16

2007-10-16

Hoang, Huan (Department: 2827)

Static information storage and retrieval

Read/write circuit

Including level shift or pull-up circuit

C365S148000, C365S230060

Reexamination Certificate

active

11045786

ABSTRACT:
A semiconductor memory device comprises a column readout voltage supply circuit which supplies a predetermined first voltage when readout is selected and supplies a predetermined second voltage which is different from the fist voltage when the readout is not selected, to each column selection line, a row readout voltage supply circuit which supplies the second voltage to each row selection line at the time of readout, a sense circuit which detects a current flowing in the selected row selection line separately from a current flowing in the non-selected row selection lines to detect an electric resistance state of the selected memory cell at the time of readout, and a column voltage displacement prevention circuit which prevents displacement of a supplied voltage level for each of the non-selected column selection lines at the time of readout.

REFERENCES:
patent: 6621729 (2003-09-01), Garni et al.
patent: 2003/0031045 (2003-02-01), Hosotani
patent: 2004/0003191 (2004-01-01), Minne
patent: 2004/0012996 (2004-01-01), Tanizaki
patent: 0 399 362 (1990-11-01), None
patent: 0 399 362 (1990-11-01), None
patent: 1 152 429 (2001-11-01), None
patent: 1 152 429 (2001-11-01), None
patent: 2002-008369 (2002-01-01), None
European Search Report mailed on Oct. 13, 2005 for European Patent Application No. 05250434.7, 4 pages.
European Search Report mailed Nov. 30, 2005 for European Patent Application No. 05250434.7, three pages.

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