Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2007-10-02

2007-10-02

Dinh, Son (Department: 2824)

Static information storage and retrieval

Read/write circuit

Noise suppression

C365S207000, C365S189050

Reexamination Certificate

active

11444487

ABSTRACT:
A semiconductor memory device has first and second sense nodes which are provided corresponding to first and second bit lines, and a sense amplifier which is connected to the first and second sense nodes and senses data read out from a memory cell, wherein the sense amplifier includes an initial sense circuit which increases a potential difference between the first and second sense nodes in a first period after beginning sense operation, and a latch circuit which increases and holds the potential difference between the first and second sense nodes in a second period after the first period, wherein the initial sense circuit includes first and second transistors of first conductive type, third and fourth transistors of first conductive type, and fifth and sixth transistors of first conductive type, wherein the latch circuit includes seventh and eighth transistors of first conductive type, and ninth and tenth transistors of second conductive type.

REFERENCES:
patent: 6567330 (2003-05-01), Fujita et al.
patent: 6781903 (2004-08-01), Mangyo et al.
patent: 7023752 (2006-04-01), Ohsawa
patent: 2005/0232043 (2005-10-01), Ohsawa
patent: 2006/0044794 (2006-03-01), Hatsuda et al.
patent: 2006/0274590 (2006-12-01), Fujita et al.
Takashi Ohsawa, et al., “An 18.5ns 128Mb SOI DRAM with a Floating Body Cell”, ISSCC Digest of Technical Papers, Session 25, Dynamic Memory, 25.1, Feb. 9, 2005, pp. 458-459.
U.S. Appl. No. 11/673,750, filed Feb. 12, 2007, Ohsawa.
U.S. Appl. No. 11/680,999, filed Mar. 1, 2007, Fujita.

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