Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2007-02-27

2007-02-27

Phung, Anh (Department: 2824)

Static information storage and retrieval

Read/write circuit

Data refresh

C365S227000, C365S228000

Reexamination Certificate

active

11154625

ABSTRACT:
A semiconductor memory device including an on-chip ECC circuit and having a data retention mode which includes, in the order of state transition, an encoding state EEST by an error correction circuit in which the error correction circuit carries out calculation of parity bits of data of the memory cells, a burst self-refresh state BSST in which the memory cells are self-refreshed in a burst with a period shorter than in ordinary self-refresh, a power-off state PFST in which an internal power supply circuit is partially turned off, a power-on state PNST in which the internal power supply circuit, partially turned off, is turned on, and a decoding state EDST by the error correction circuit in which the error correction circuit corrects errors of the memory cells. In case a command for exiting from the data retention mode in the encoding state, transition may be made to an idle state IST so that re-entry may be made from the decoding state EDST to the BSST.

REFERENCES:
patent: 6697992 (2004-02-01), Ito et al.
patent: 6795362 (2004-09-01), Nakai et al.
patent: 6965537 (2005-11-01), Klein et al.
patent: 7085152 (2006-08-01), Ellis et al.
patent: 2002-56671 (2002-02-01), None
patent: 2003-68076 (2003-03-01), None

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