Semiconductor memory device

Static information storage and retrieval – Read/write circuit – Differential sensing

Reexamination Certificate

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C365S189070

Reexamination Certificate

active

11266408

ABSTRACT:
There provided a semiconductor memory device which ensures writing to all memory cells regardless of fluctuations in properties of the memory cells caused by manufacturing error or the like and can reduce write operation time and power consumption. Write operations for a memory cell1and a dummy memory cell1aare controlled based on a write amplifier control signal WAE. Write operation end timing is determined based on a write completion signal WRST which indicates a storage state of the dummy memory cell1a. The dummy memory cell1aand peripheral circuitry are designed so that write time required for the dummy memory cell1ais more than or equal to a maximum of write time required for the memory cells1.

REFERENCES:
patent: 6201757 (2001-03-01), Ward et al.
patent: 6392957 (2002-05-01), Shubat et al.
patent: 6556472 (2003-04-01), Yokozeki
patent: 6999367 (2006-02-01), Yamagami
patent: 09-147574 (1997-06-01), None
patent: 11-096768 (1999-04-01), None
patent: 2002-367377 (2002-12-01), None

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