Semiconductor memory device

Static information storage and retrieval – Read/write circuit – Data refresh

Reexamination Certificate

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C365S228000

Reexamination Certificate

active

07120076

ABSTRACT:
There is disclosed a semiconductor memory device which comprises a plurality of bit line pairs each having first and second bit lines arranged in a first direction, a cell array having a plurality of SRAM cells each of which is connected between the first and second bit lines of a corresponding bit line pair via first and second storage nodes, respectively, a plurality of word lines arranged in a second direction crossing the first direction, and a data write circuit which, in the write mode, writes data into an SRAM cell selected by a word line via the first and second bit lines and, in the read mode, rewrites data read onto the first bit line from an SRAM cell selected by a word line onto the first bit line.

REFERENCES:
patent: 5724292 (1998-03-01), Wada
patent: 6064616 (2000-05-01), Ciraula et al.
patent: 6711051 (2004-03-01), Poplevine et al.
patent: 2004/0264279 (2004-12-01), Wordeman et al.
patent: 6-195977 (1994-07-01), None
U.S. Appl. No. 10/916,524, filed Aug. 12, 2004, Sugahara et al.

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