Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate
2006-12-19
2006-12-19
Auduong, Gene N. (Department: 2827)
Static information storage and retrieval
Read/write circuit
Bad bit
C365S230030, C365S189011
Reexamination Certificate
active
07151704
ABSTRACT:
Provided are a memory cell array, a column gate array, a row decoder, a column decoder, a sense amplifier array, a read data bus, an output buffer, and a redundancy discrimination signal bus. In the case of redundancy replacement, the output buffer outputs read data excluding the read data of a memory cell block serving as an object of redundancy replacement. In the case of no redundancy replacement, the output buffer outputs read data excluding the read data of a redundant memory cell block. Then, the read data excluded by the output buffer is provided to the output buffer as an output enable signal. The transition timing of the read data excluded by the output buffer is set to be later than that of the other read data.
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Auduong Gene N.
Stevens Davis Miller & Mosher LLP
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