Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2006-11-14

2006-11-14

Auduong, Gene N. (Department: 2827)

Static information storage and retrieval

Systems using particular element

Flip-flop

C365S189090, C365S226000

Reexamination Certificate

active

07136297

ABSTRACT:
An SRAM includes: a memory cell array; and a control circuit. Each memory cell includes: inverters; and access transistors interposed in lines connecting internal nodes in the respective inverters and a pair of bit lines BIT and NBIT. The control circuit includes a bias circuit for transmitting signals to the bit lines BIT and NBIT. A memory cell power supply terminal and a control circuit power supply terminal are isolated from each other. When power is turned on, the bias circuit sets one of the bit lines at a power supply potential (high potential) and the other bit line at a ground potential, so that a minute potential difference is generated between the internal nodes and thereby data is initialized. Transistors in the memory cell do not need to be asymmetric.

REFERENCES:
patent: 5472899 (1995-12-01), Hsue et al.
patent: 6212094 (2001-04-01), Rimondi
patent: 6707707 (2004-03-01), Marr
patent: 1-113995 (1989-05-01), None

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