Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

1997-07-23

1999-08-24

Yoo, Do Hyun

Static information storage and retrieval

Read/write circuit

Including level shift or pull-up circuit

36518909, 365207, 365226, G11C 700

Patent

active

059432730

ABSTRACT:
Drains of first and second transistors are connected to a low level line of an internal circuitry such as a sense amplifier related to determination of a potential in a memory cell. The first transistor has its gate diode-connected to a sense drive line and its source grounded. The second transistor receives at its gate an internally generated signal, and its source is grounded. In the standby state, the potential of the sense drive line is set higher than low level of said word lines by the threshold voltage Vthn of the first transistor and used as dummy GND potential Vss', and in the active state, the second transistor is rendered conductive so as to prevent floating of the sense drive line from the dummy GND potential Vss'.

REFERENCES:
patent: 4679172 (1987-07-01), Kirsch et al.
patent: 5299154 (1994-03-01), Oowaki et al.
patent: 5444659 (1995-08-01), Yokokura
patent: 5446697 (1995-08-01), Yoo et al.
patent: 5687123 (1997-11-01), Hidaka et al.
ISSC 89/Digest of Technical Papers, Feb. 17, 1989, pp. 248-249.

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