Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2006-04-11

2006-04-11

Elms, Richard (Department: 2824)

Static information storage and retrieval

Read/write circuit

Differential sensing

C365S148000, C365S189090

Reexamination Certificate

active

07027342

ABSTRACT:
In a semiconductor memory device having a crosspoint-type memory cell array, each reference level between two adjacent memory levels when memory levels of multi-level information stored in a memory cell are arranged in order of size of resistance values of a corresponding variable resistive element is defined by a reference current in a middle state between a first and a second current states. In the first current state, a readout current of high resistance selected cell in which the resistance is higher in the two adjacent memory levels becomes the largest state depending on a distribution pattern of a resistance state of the other unselected cell. In the second current state, a readout current of low resistance selected cell in which the resistance is lower in the two adjacent memory levels becomes a smallest state depending on a distribution pattern of a resistance state of the other unselected memory cell.

REFERENCES:
patent: 6314014 (2001-11-01), Lowrey et al.
patent: 6778420 (2004-08-01), Parkinson
patent: 6781860 (2004-08-01), Parkinson
patent: 2005/0169038 (2005-08-01), Inoue et al.
patent: 2005/0276091 (2005-12-01), Inoue
patent: 2002-8369 (2002-01-01), None

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