Semiconductor memory device

Static information storage and retrieval – Addressing – Multiple port access

Reexamination Certificate

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C365S063000, C365S230060

Reexamination Certificate

active

07110318

ABSTRACT:
A semiconductor memory device having a multiport memory includes a plurality of memory cells MC arranged in columns and rows, a plurality of first word lines WLA0–WLAn connected to a first port13a, and a plurality of second word lines WLB0–WLBn connected to a second port13b. Each of a plurality of first word lines WLA0–WLAn and each of a plurality of second word lines WLB0–WLBn are arranged alternately in a planar layout. A semiconductor memory device is thus obtained that allows a coupling noise between interconnections to be reduced without an increase in memory cell area.

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patent: P2002-237539 (2002-08-01), None

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