Semiconductor memory device

Static information storage and retrieval – Read/write circuit – Testing

Reexamination Certificate

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C365S185260

Reexamination Certificate

active

07075839

ABSTRACT:
A memory cell array includes a memory cell region composed of memory cells and a sample cell region composed of word line sample cells and bit line sample cells. The word line sample cell and the bit line sample cell are formed so that by a voltage applied to word lines and bit lines, charge transfer from the floating gate electrode occurs more easily than the memory cell.

REFERENCES:
patent: 5268869 (1993-12-01), Ferris et al.
patent: 5408433 (1995-04-01), Hashimoto
patent: 6414890 (2002-07-01), Arimoto et al.
patent: 6444514 (2002-09-01), Nishimoto et al.
patent: 6646911 (2003-11-01), Hidaka
patent: 2004/0145959 (2004-07-01), Kuge et al.
patent: 10-302498 (1998-11-01), None

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