Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2006-07-11

2006-07-11

Baker, Stephen M. (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

C714S772000, C714S773000

Reexamination Certificate

active

07076722

ABSTRACT:
An ECC circuit (103) is located between I/O terminals (1040–1047) and page buffers (1020–1027). The ECC circuit (103) includes a coder configured to generate check bits (ECC) for error correcting and attach the check bits to data to be written into a plurality of memory cell areas (1010–1017), and a decoder configured to employ the generated check bits (ECC) for error correcting the data read out from the memory cell areas (1010–1017). The ECC circuit (103) allocates a set of 40 check bits (ECC) to an information bit length of 4224=(528×8) bits to execute coding and decoding by parallel processing 8-bit data, where data of 528 bits is defined as a unit to be written into and read out from one memory cell area (101j).

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