Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2005-12-27

2005-12-27

Phan, Trong (Department: 2827)

Static information storage and retrieval

Read/write circuit

C365S189040, C365S207000

Reexamination Certificate

active

06980474

ABSTRACT:
A semiconductor memory device disclosed herein has a memory cell array in which memory cells are arranged in a matrix form, data being written into each of the memory cells by passing a cell current therethrough; word lines which are provided in parallel along a row direction in the memory cell array; bit lines which are provided in parallel along a column direction in the memory cell array, the column direction being crossed with the row direction; sense amplifiers which are respectively connected to the bit lines and which write data held in the sense amplifiers into the memory cells; a data line which supplies data to be written into the sense amplifiers; and a control circuit which, in a continuous write operation of performing write operations by continuously switching a column address to select a column, opens only a connection between the sense amplifier selected by the column address and the bit line to write the data held in the sense amplifier into the memory cell.

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patent: 6400640 (2002-06-01), Woo et al.
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patent: 2002-246571 (2002-08-01), None
patent: 2003-68877 (2003-03-01), None
Takashi Ohsawa, et al., “Memory Design Using One-Transistor Gain Cell on SOI”, 2002 IEEE International Solid-State Circuits Conference, 2002, pp. 152-153, and 454.
U.S. Appl. No. 10/882,354, filed Jul. 2, 2004, Ohsawa.
U.S. Appl. No. 10/891,000, filed Jul. 15, 2004, Ohsawa.
U.S. Appl. No. 10/901,237, filed Jul. 29, 2004, Ohsawa.

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