Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2005-10-11

2005-10-11

Flynn, Nathan J. (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S296000, C257S311000, C257S314000, C257S321000, C365S063000

Reexamination Certificate

active

06953960

ABSTRACT:
A first level metal interconnection line in a layer below a third level metal interconnection line serving as a main word line MWL is used as a shunting interconnection line and electrically connected to a first level polysilicon interconnection line constituting a sub word line SWL at prescribed intervals. By applying a hierarchical word line structure and a word line shunting structure both, a word line is driven into a selected state at high speed without increasing an array occupancy area and manufacturing steps.

REFERENCES:
patent: 5748549 (1998-05-01), Kometani et al.
patent: 5903492 (1999-05-01), Takashima
patent: 5963467 (1999-10-01), Miyatake et al.
patent: 6240006 (2001-05-01), Kawasaki
patent: 3-265167 (1991-11-01), None
patent: 8-340089 (1996-12-01), None
patent: 11354745 (1999-12-01), None

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