Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2005-02-15

2005-02-15

Tran, M. (Department: 2818)

Static information storage and retrieval

Read/write circuit

Signals

Reexamination Certificate

active

06856559

ABSTRACT:
Parasitic capacitances formed between bit lines to which signals are to be read out of memory cells and a signal transmission line arranged above them are to be reduced. Second complementary global bit lines for transmitting data read out of memory cells MC via complementary bit lines are arranged above a memory cell array. Each second global bit line is so arranged that a triangle having as its vertexes the center of the section of one of the complementary bit lines, that of the section of the other and that of the section of the second global bit line arranged directly above these complementary bit lines be an isosceles triangle.

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Prince, Betty, “Semiconductor Memories”, 1983, Wiley, 2ndedition, pp. 286-287.

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