Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2005-03-29

2005-03-29

Lam, David (Department: 2818)

Static information storage and retrieval

Read/write circuit

Including level shift or pull-up circuit

C365S185180, C365S189090

Reexamination Certificate

active

06873554

ABSTRACT:
There is provided a semiconductor memory device capable of eliminating the occurrence of delays in access when switching from a standby state to an active state. A drain voltage generator10A generates a predetermined drain voltage MCD which is low in driving performance owing to PMOS15, 17and NMOS16, 18each having large ON resistance irrespective of the presence of a chip selection signal and apply the drain voltage to each of memory arrays. When read operation is started when a chip selection signal /CE goes “L”, the drain voltage MCD is generated by PMOSs11, 15and NMOSs12to14with a predetermined driving performance. As a result, a predetermined drain voltage MCD is always applied when switching from a standby state to an active state, thereby eliminating the occurrence of delays in access to a memory cell.

REFERENCES:
patent: 6233177 (2001-05-01), Shokouhi et al.
patent: 06-215585 (1994-08-01), None
patent: 06-342598 (1994-12-01), None
patent: 2000-011668 (2000-01-01), None

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