Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2005-07-12

2005-07-12

Auduong, Gene N. (Department: 2818)

Static information storage and retrieval

Read/write circuit

Data refresh

C365S230060, C365S230080

Reexamination Certificate

active

06917553

ABSTRACT:
In a semiconductor memory device equipped with a memory cell array in which dynamic memory cells are arrayed, for example, in a matrix, a technique speeds up of a read operation. In the read cycle, an external access controller outputs an external access execution timing signal which changes to active after the change of the output enable signal to active, and changes to inactive after a start of the latch of the read signal caused by changes of the latch signal to active and inactive. In the read cycle, the refresh controller outputs the refresh execution timing signal which changes to active according to the change of the latch signal to active while the refresh requirement signal is active, and stays active for a predetermined time period.

REFERENCES:
patent: 6288728 (2001-09-01), Satoh et al.
patent: 6336180 (2002-01-01), Long et al.
patent: 6421754 (2002-07-01), Kau et al.
patent: 6597615 (2003-07-01), Mizugaki
patent: a 2002-74945 (2002-03-01), None

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