Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2005-07-26

2005-07-26

Auduong, Gene N. (Department: 2827)

Static information storage and retrieval

Systems using particular element

Flip-flop

C257S369000, C257S903000

Reexamination Certificate

active

06922354

ABSTRACT:
Positive
egative bit lines are arranged on a second-layer interconnection the VDD power supply interconnection is arranged between the positive
egative bit lines, the word line is arranged on a third-layer interconnection, and the VSS power supply interconnection is arranged on a fourth-layer interconnection. Alternatively, the word line is arranged on the second-layer interconnection, the positive
egative bit lines are arranged on the third-layer interconnection, the VDD power supply interconnection is arranged between the positive
egative bit lines, and the VSS power supply interconnection is arranged on the fourth-layer interconnection. Alternatively, the VDD power supply interconnection is arranged on the second-layer interconnection, the positive
egative bit lines are arranged on the third-layer interconnection, the word line is arranged on the fourth-layer interconnection, and the VSS power supply interconnection is arranged on the fifth-layer interconnection.

REFERENCES:
patent: 5930163 (1999-07-01), Hara et al.
patent: 6417549 (2002-07-01), Oh
patent: 6479860 (2002-11-01), Ohbayashi
patent: 6597041 (2003-07-01), Ohbayashi
patent: 6677649 (2004-01-01), Osada et al.
patent: 6750555 (2004-06-01), Satomi et al.
patent: 10178110 (1998-06-01), None

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