Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2005-09-06

2005-09-06

Le, Vu A. (Department: 2824)

Static information storage and retrieval

Systems using particular element

Flip-flop

C365S156000

Reexamination Certificate

active

06940746

ABSTRACT:
A semiconductor memory device includes first and second CMOS (complementary metal oxide semiconductor) inverter circuits each having a latch structure and a control transistor which is connected between a storage node of the first CMOS inverter circuit and a bit line and whose gate is connected to a word line. The device further includes a selection circuit to apply one of a first voltage and a second voltage different from the first voltage to a power supply node of at least the second CMOS inverter circuit. The selection circuit applies the second voltage to the power supply node of the second CMOS inverter circuit at least in “1” data write mode.

REFERENCES:
patent: 4189785 (1980-02-01), Rapp
patent: 5375086 (1994-12-01), Wahlstrom
patent: 5831896 (1998-11-01), Lattimore et al.
patent: 2003/0147271 (2003-08-01), Jo
Hiep Tran, “Demonstration of 5T SRAM and 6T Dual-Port RAM Cell Arrays”, 1996 Symposium on VLSI Circuits Digest of Technical Papers, 1996,pp. 68-69.

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