Semiconductor memory device

Static information storage and retrieval – Read/write circuit – Signals

Reexamination Certificate

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C365S233100, C365S200000

Reexamination Certificate

active

06876587

ABSTRACT:
A semiconductor memory device comprises a memory cell array, a decoder unit selecting a word line of the memory cell array, a first dummy cell array connected to a first dummy bit line and disposed with the memory cell array at a first location away from the decoder unit along the word line, a second dummy cell array connected to second dummy bit lines and disposed with the memory cell array at a second location away from the decoder unit along the word line, the second location being farther from the decoder unit than the first location, and a timing control unit determining timing of activation and deactivation of an internal control signal.

REFERENCES:
patent: 5550781 (1996-08-01), Sugawara et al.
patent: 20040114424 (2004-06-01), Yoshida
patent: 11-096768 (1999-04-01), None
patent: 11-203873 (1999-07-01), None

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