Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2005-05-03

2005-05-03

Tran, M. (Department: 2818)

Static information storage and retrieval

Read/write circuit

Flip-flop used for sensing

C365S177000

Reexamination Certificate

active

06888770

ABSTRACT:
A semiconductor memory device includes: a device substrate having a semiconductor layer separated by a dielectric layer from a base substrate; a memory cell array having a plurality of memory cells formed and arranged on the semiconductor layer of the device substrate, each the memory cell having a MOS transistor structure with a body in an electrically floating state to store data based on a majority carrier accumulation state of the body; and a sense amplifier circuit configured to perform data read out of the memory cell array, the sense amplifier circuit including a bipolar transistor for performing current amplification of a memory cell selected during data reading.

REFERENCES:
patent: 4658159 (1987-04-01), Miyamoto
patent: 4984207 (1991-01-01), Tateno et al.
patent: 5036231 (1991-07-01), Kanbara
patent: 5371703 (1994-12-01), Miyamoto
patent: 6538916 (2003-03-01), Ohsawa
T. Shino, et al., IEEE Translations on Electron Devices, vol. 49, No. 3, pp. 414-421, “Analysis on High-Frequency Characteristics Of SOI Lateral BJTs with Self-Aligned External Base For 2-GHz RF Applications”, Mar. 2002.

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