Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2005-04-05

2005-04-05

Elms, Richard (Department: 2824)

Static information storage and retrieval

Read/write circuit

Data refresh

C365S195000, C365S233500

Reexamination Certificate

active

06876592

ABSTRACT:
A semiconductor memory device capable of accelerating address access and shortening cycle time is provided. A first address decoder (2) and first refresh address decoder (5) respectively decode an external address (Xn) supplied from outside the semiconductor memory device and a refresh address (RXn) used for refreshing within the semiconductor memory device. A multiplexer (8) selects the external address side decode signal (XnDm) or the refresh address side decode signal (XnRm) and outputs the signal as a decode signal (XnMm) based on an external address transmission signal (EXTR) and refresh address transmission signal (RFTR) so that a refresh operation and a read/write operation is performed continuously within one memory cycle. A word driver (10) then decodes decode signals (XnMm, XpMq) selected with multiplexer (8) and so forth, and activates a word line (WLmq).

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