Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

1996-09-13

1999-03-02

Zarabian, A.

Static information storage and retrieval

Systems using particular element

Capacitors

36518909, 36518508, G11C 1124

Patent

active

058779787

ABSTRACT:
In a dynamic random access memory, at a time of body-refresh operation, a bit-line potential VBL is set to a body-refresh-potential VBR, and the body-refresh-potential VBR is supplied to bit-line pairs via a bit-line precharging/equalizing circuit 111c, thereby the charge accumulated in the body of the n channel MOS transistor 72cb in a memory cell is drained to the bit-line pairs.

REFERENCES:
patent: 4807194 (1989-02-01), Yamada et al.
patent: 5471421 (1995-11-01), Rose et al.
Konishi et al., "A 38-ns 4-Mb DRAM with a Battery-Backup (BBU) Mode," IEEE Journal of Solid-State Circuits, vol. 25, No. 5 (Oct. 1990), pp. 1112-1117.
Asakura et all, "An Experimental 256-Mb DRAM with Boosted Sense-Ground Scheme," IEEE Journal of Solid-State Circuits, vol. 29, No.11 (Nov. 1994), pp. 1303-1308.
Morishita et al. "Leakage Mechanism due to Floating Body and Countermeasure on Dynamic Rentention mode of SOI-DRAM," 1995 Symposium on VLSI Technology Digest of Technical Papers, pp. 141-142 (Apr., 1995).
Maeda et al., "A Vertical .PHI.-Shape Transistor (V.PHI.T) Cell of 1Gbit DRAM and Beyond," 1994 Symposium on VLSI Technology Digest of Technical Papers, pp. 133-134 (Apr., 1994).
Yamagata et al., "Circuit Design Techniques for Low-Voltage Operating and/or Giga-Scale DRAMs," 1995 IEEE International Solid-State Circuits Conference Digest of Technical Papers, pp. 248-249 (Jan., 1995).

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