Semiconductor memory device

Static information storage and retrieval – Systems using particular element – Flip-flop

Reexamination Certificate

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Details

C365S230050, C365S042000, C365S042000, C257S200000, C257S321000, C257S369000

Reexamination Certificate

active

06868001

ABSTRACT:
With a P well region being divided, NMOS transistors N1and N3are formed in the first P well region, and NMOS transistors N2and N4in the second P well region. Alternatively, with a N well region being divided, PMOS transistor P1is formed in the first N well region, and PMOS transistor P2in the second N well region.

REFERENCES:
patent: 5049967 (1991-09-01), Watanabe et al.
patent: 6590802 (2003-07-01), Nii
patent: 20020181273 (2002-12-01), Nii et al.
patent: 10-178100 (1998-06-01), None
patent: 11-135647 (1999-05-01), None
patent: 2000-36543 (2000-02-01), None
patent: 2000-036543 (2000-02-01), None
patent: 2001-28401 (2001-01-01), None

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