Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2005-09-27

2005-09-27

Thompson, Craig A. (Department: 2813)

Static information storage and retrieval

Read/write circuit

Differential sensing

C257S072000, C257SE21444

Reexamination Certificate

active

06950362

ABSTRACT:
A semiconductor memory device capable of enhancing a production yield is provided. A dummy control circuit activates a first dummy column including a plurality of dummy cells placed at a position close to a row decoder in a row direction and a second dummy column including a plurality of dummy cells placed at a position farthest from the row decoder in a row direction with a plurality of memory cells interposed between the first dummy column and the second dummy column, through first and second dummy word lines. A dummy column selector selects either one of a signal on a first dummy bit line connected to the first dummy column and a signal on a second dummy bit line connected to the second dummy column, and outputs the selected signal to an amplifier control circuit. The amplifier control circuit generates an amplifier startup signal with respect to an amplifier circuit based on a signal from the dummy column selector.

REFERENCES:
patent: 6212117 (2001-04-01), Shin et al.
patent: 6298004 (2001-10-01), Kawasaki et al.
patent: 6434074 (2002-08-01), Brown
Osada, et al., “Univeral-Vhd dd0.65-2.0-V 32-kB Cache Using a Voltage-Adapted Timing-Generation Scheme and a Lithography Symmetrical Cell”, Journal of Solid-State Circuites, vol. 36, no. 11, Nov., 2001, pp. 1738-1744.

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