Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2002-09-04

2004-06-15

Tran, M. (Department: 2818)

Static information storage and retrieval

Systems using particular element

Capacitors

C365S230030

Reexamination Certificate

active

06751116

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory device such as DRAM (Dynamic Random Access Memory).
A semiconductor memory device called DRAM requires rewriting of memory cells and precharging of bit lines in every cycle time. Therefore, the cycle time required by the DRAM is about twice the access time. There is technology for reducing the cycle time to approximately the same length as that of the access time by apparently hiding precharge operation of the bit lines. One example of this technology is to cause two internal ports to interleave with each other by using the memory cells each including two transistors and a single capacitor.
FIG. 19
schematically shows the structure of a DRAM using this technology. Each memory cell MC
1
to MC
4
of the DRAM includes two transistors Ta, Tb and a single capacitor C. This DRAM causes the following two ports A, B to interleave with each other: the port A formed by the path including transistor Ta, bit line BLa
1
or BLa
2
, data bus DBa, and read amplifier and write driver
1103
a
; and the port B formed by the path including transistor Tb, bit line BLb
1
or BLb
2
, data bus DBb, and read amplifier and write driver
1103
b
. Hereinafter, interleave operation will be described regarding the case where data is read from a memory cell.
A row decoder
1101
activates a word line WLa
1
, whereby the transistors Ta of the memory cells MC
1
, MC
3
are turned ON. As a result, data stored in the capacitors C of the memory cells MC
1
, MC
3
are read to the bit lines BLa
1
, BLa
2
and then amplified by a sense amplifier (not shown). A column decoder
1102
a
selects the bit line BLa
1
and connects the bit line BLa
1
to the data bus DBa. As a result, the data read from the memory cell MC
1
to the bit line BLa
1
is transferred to the data bus DBa. The data read to the bit lines BLa
1
, BLa
2
are rewritten to the memory cells MC
1
, MC
3
. The row decoder
1101
then inactivates the word line WLa
1
, whereby the transistors Ta of the memory cells MC
1
, MC
3
are turned OFF. The bit lines BLb
1
, BLb
2
are precharged during the above operation.
The data transferred to the data bus DBa is amplified by the read amplifier and write driver
1103
a
for output to an input/output (I/O) buffer
1104
. The I/O buffer
1104
outputs the amplified data to the outside. On the other hand, the row decoder
1101
activates a word line WLb
2
, whereby the transistors Tb of the memory cells MC
2
, MC
4
are turned ON. As a result, data stored in the capacitors C of the memory cells MC
2
, MC
4
are read to the bit lines BLb
1
, BLb
2
and amplified by a sense amplifier (not shown).
A column decoder
1102
b
selects the bit line BLb
1
and connects the bit line BLb
1
to the data bus DBb. As a result, the data read from the memory cell MC
2
to the bit line BLb
1
is transferred to the data bus DBb. The data read to the bit lines BLb
1
, BLb
2
are rewritten to the memory cells MC
2
, MC
4
. The row decoder
1101
then inactivates the word line WLb
2
, whereby the transistors Tb of the memory cells MC
2
, MC
4
are turned OFF. The bit lines BLa
1
, BLa
2
are precharged during the above operation.
The data transferred to the data bus DBb is amplified by the read amplifier and write driver
1103
b
for output to the I/O buffer
1104
. The I/O buffer
1104
outputs the amplified data to the outside.
Such interleave operation of the two internal ports apparently hides precharge operation of the bit lines, thereby reducing the cycle time to approximately the same length as that of the access time.
The DRAM of
FIG. 19
has a read amplifier and write driver for each port. In other words, the DRAM of
FIG. 19
has a read amplifier and write driver
1103
a
for the port A and a read amplifier and write driver
1103
b
for the port B. This increases the area of peripheral circuitry including the read amplifiers and write drivers if a specification using a large bit width is required (e.g., an embedded DRAM).
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a semiconductor memory device enabling reduction in layout area.
According to one aspect of the present invention, a semiconductor memory device includes a plurality of memory cells, a plurality of first and second word lines, and a plurality of first and second bit lines. The plurality of memory cells are arranged in rows and columns. The plurality of first and second word lines are arranged in the rows. The plurality of first and second bit lines are arranged in the columns. Each of the plurality of memory cells includes a first transistor, a second transistor and a capacitor. The first transistor is connected between a corresponding first bit line and the capacitor and receives a voltage on a corresponding first word line at its gate. The second transistor is connected between a corresponding second bit line and the capacitor and receives a voltage on a corresponding second word line at its gate. The semiconductor memory device further includes a data line, a plurality of first and second column selection switches, a word line driver, a column selection circuit, an input/output (I/O) buffer, and a data transfer circuit. The plurality of first column selection switches are provided corresponding to the plurality of first bit lines, and each connects and disconnects a corresponding first bit line to and from the data line. The plurality of second column selection switches are provided corresponding to the plurality of second bit lines, and each connects and disconnects a corresponding second bit line to and from the data line. The word line driver drives first and second word lines corresponding to a memory cell to be accessed. The column selection circuit turns ON/OFF first and second column selection switches corresponding to the memory cell to be accessed. The I/O buffer receives and outputs data from and to the outside. The data transfer circuit transfers data read from a memory cell to the data line to the I/O buffer and transfers write data from the I/O buffer to the data line. The word line driver and the column selection circuit conduct interleave operation, and the data transfer circuit and the I/O buffer do not conduct interleave operation.
In the above semiconductor memory device, peripheral circuitry including the data transfer circuit is required for only one port, thereby enabling reduction in layout area.
Preferably, the data line includes a write data line and a read data line. Each of the plurality of first and second column selection switches connects and disconnects a corresponding bit line to and from the write data line in order to write data to a memory cell. Each of the plurality of first and second column selection switches connects and disconnects the corresponding bit line to and from the read data line in order to read data from a memory cell.
In the above semiconductor memory device, the read data line need only be controlled for read operation, and the write data line need only be controlled for write operation. This facilitates control of the write data line and the read data line and timing design as compared to the case where a single data line is controlled for both read and writ operations.
Preferably, the data line is a single-type data line. The above semiconductor memory device eliminates the need to consider precharge operation of the bit lines, enabling quick design.
According to another aspect of the present invention, a semiconductor memory device includes a plurality of memory cells, a plurality of first and second word lines, and a plurality of first and second bit lines. The plurality of memory cells are arranged in rows and columns. The plurality of first and second word lines are arranged in the rows. The plurality of first and second bit lines are arranged in the columns. Each of the plurality of memory cells includes a first transistor, a second transistor and a capacitor. The first transistor is connected between a corresponding first bit line and the capacitor and receives a voltage on a corres

Affiliated with

Also associated with

Rating

Semiconductor memory device does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor memory device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory device will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3363476