Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2002-10-01

2004-02-24

Dinh, Son T. (Department: 2824)

Static information storage and retrieval

Interconnection arrangements

C365S051000

Reexamination Certificate

active

06697278

ABSTRACT:

TECHNICAL FIELD
The present invention relates generally to a semiconductor memory device such as a SRAM (Static Random Access Memory) and more particularly to semiconductor memory device that may be capable of reducing a propagation time difference among all memory cells in a memory cell region.
BACKGROUND OF THE INVENTION
In a semiconductor memory device such as a SRAM (Static Random Access Memory), it is desirable to provide a large memory capacity, high-speed operation, reduced manufacturing costs, and the like. In order to provide these features, miniaturization of the semiconductor device components is rapidly being advanced.
Referring now to
FIG. 30
, a circuit schematic diagram of a conventional semiconductor memory device is set forth and given the general reference character
10
. Conventional semiconductor memory device
10
is a SRAM and includes word lines (WL
1
to WLn) extending in a row direction and bit lines (BL
1
-BLm and /BL
1
-/BLm) extending in a column direction. A plurality of memory cells
11
are placed at intersections of word lines WL and bit lines (BL and /BL) to form a matrix pattern. Conventional semiconductor memory device
10
includes a plurality of select circuits
12
and a plurality of reading circuits
13
. Each select circuit
12
is connected to an associated word line WL. Each reading circuit
13
is connected to an associated bit line pair (BL and /BL). Bit lines (BL
1
-BLm and /BL
1
-/BLm) form bit line pairs, where BL indicates a true bit line and /BL indicates a complement bit line in a bit line pair (“/” indicates an inversion signal).
In semiconductor memory device
10
, select circuit
12
provides a select signal on a word line WL to select a memory cell
11
. Data (memory information) is read from the selected memory cell
11
by a reading circuit
13
connected to a bit line pair (BL and /BL). The distance from the memory cell
11
to a select circuit
12
and/or a reading circuit
13
varies depending on the location of the memory cell
11
selected. For that reason, when a select signal is to be transmitted to a group of memory cells
11
connected to the same word line WL, the timing of the memory cell
11
providing data (response speed) to a bit line pair (BL and /BL) varies between memory cells
11
of the group that are positioned far from the select circuit
12
(hereinafter referred to as distal side) and memory cells
11
of the group that are positioned near the select circuit
12
(hereinafter referred to as proximal side). A difference in response speed corresponds to a delay time due to parasitics (resistance and capacitance) or the word line WL. As a result, the reading speed between memory cells
11
varies.
Similarly, of a group of memory cells
11
connected to the same bit line pair (BL and /BL), the reading speed is varied due to bit line parasitics (resistance and capacitance) between distal side memory cells
11
and proximal side memory cells
11
with respect to a corresponding reading circuit
13
. Accordingly, semiconductor memory device
10
is designed based on data propagation time of distal side memory cells
11
in order to avoid malfunction irrespective of whether the selected memory cell is a distal side memory cell
11
or a proximal side memory cell
11
.
A more detailed description of problems of a conventional semiconductor memory device will now be given using a reading circuit in an SRAM as an example.
Referring now to
FIG. 31
, a circuit schematic diagram of a conventional memory cell block is set forth. The conventional memory cell block has n memory cells
11
that are connected to the same reading circuit
13
through a bit line pair (BL and /BL). The distance from reading circuit
13
is different for each memory cell
11
. The parasitic resistance and parasitic capacitance of bit line pair (BL and /BL) causes the propagation time of data to vary from one memory cell
11
to another memory cell
11
. The timing T of an activation signal for reading circuit
13
is set for a worst case memory cell
11
to provide an electrical potential difference &Dgr;V necessary at bit line pair (BL and /BL) for a normal operation of reading circuit
13
. In this case, the worst case memory cell
11
can be the distal memory cell
11
with respect to reading circuit
13
.
The delay of data signal transmission due to differences in distance from reading circuit
13
in a conventional memory cell block will now be described with reference to FIG.
32
. FIG.
32
(
a
) is a circuit schematic diagram of a conventional memory cell block illustrating current paths. FIG.
32
(
b
) is a waveform diagram showing the electric potential waveform of bit lines when a proximal side memory cell is selected. FIG.
32
(
c
) is a waveform diagram showing the electric potential waveform of bit lines when a distal side memory cell is selected.
As shown in FIG.
32
(
a
), a proximal memory cell
11
1
with respect to reading circuit
13
sets the electric potential difference between bit line pair (BL and /BL) to &Dgr;V by taking a current path indicated by an arrow b. In proximal memory cell
11
1
, as illustrated in FIG.
32
(
b
), the electric potential &Dgr;V is reached at an early time because the electric resistance of bit line BL from memory cell
11
1
to reading circuit
13
is small.
On the other hand, as shown in FIG.
32
(
b
), a distal memory cell
11
n
with respect to reading circuit
13
sets the electric potential difference between bit line pair (BL and /BL) to &Dgr;V by taking a current path indicated by an arrow c. In distal memory cell
11
n
, as illustrated in FIG.
32
(
c
), the electric potential &Dgr;V is reached at a later time T because the electric resistance of bit line BL from memory cell
11
n
to reading circuit
13
is large. In this way, it can be seen that memory cell
11
n
needs more time to set an electric potential between bit line pair (BL and /BL) to &Dgr;V than proximal memory cell
11
1
.
As shown in FIG.
32
(
c
), reading circuit
13
is controlled with a timing T at which an electric potential difference &Dgr;V between a bit line pair (BL and /BL) is achieved for a read from distal memory cell
11
n
. Timing T is set to accommodate a worst-case scenario. Therefore, as illustrated in FIG.
32
(
b
), when proximal memory cell
11
1
is selected, the electric potential difference between bit line pair (BL and /BL) at time T (when reading circuit
13
is activated) is &Dgr;V+&agr;. In other words, setting timing T to accommodate distal memory cell
11
n
is not optimal for proximal memory cell
11
1
which reaches an electric potential difference &Dgr;V earlier than timing T.
FIG. 33
illustrates a conventional approach for dividing a bit line. FIG.
33
(
a
) is a circuit schematic diagram of a conventional memory cell block having 2n memory cells. FIG.
33
(
b
) is a circuit schematic diagram of a conventional memory cell block obtained by dividing the number of memory cells connected to a bit line pair (BL and /BL) in two as compared to the conventional memory cell block of FIG.
33
(
a
).
In FIG.
33
(
a
), 2n memory cells (
11
1
to
11
2n
) are connected to bit line pair (BL and /BL). In FIG.
33
(
b
), each bit line pair (of FIG.
33
(
a
)) is divided so that only n memory cells of the 2n memory cells are connected to each divided bit line pair (BL and /BL) so that time to propagate data to reading circuit
13
from a distal memory cell
11
n
becomes closer to the time to propagate data to reading circuit
13
from a proximal memory cell
11
1
.
In the example illustrated in FIG.
33
(
b
), each bit line is divided to make the distal memory cell
11
n
closer to the proximal memory cell
11
1
to reduce the difference in data propagation time to reading circuit
13
. However, the number of reading circuits
13
required has to be increased in accordance with the division multiple of the bit line (in this case, the number of reading circuits
13
must double). The increase in the number of reading circuits
13
results in the increase in chip size and thus, increases

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