Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2002-09-10

2004-08-31

Nguyen, Tan T. (Department: 2818)

Static information storage and retrieval

Read/write circuit

Bad bit

C365S225700

Reexamination Certificate

active

06785171

ABSTRACT:

CROSS REFERENCES TO RELATED APPLICATIONS
This application relies for priority upon Korean Patent Application No. 2001-55949, filed on Sep. 11, 2001, the contents of which are herein incorporated by reference in their entirety.
FIELD
The present invention relates to a semiconductor memory device having a redundancy function. Also the invention relates to a semiconductor memory device to enhance a data access speed.
BACKGROUND
As a memory unit, a memory cell must stably store data that is processed in a system. Accordingly, there is a requirement for a procedure to test respective memory cells.
A redundancy circuit is a spare circuit, built into a memory device, for replacing defective cells with redundant memory cells. When an external address addressing a defective cell is input, the redundancy circuit disables a wordline organically connected to the defective cell and accesses a redundancy memory cell corresponding to the defective cell.
A semiconductor memory device must have a function to be instantly responsive to a central processing unit (CPU) speed, which is the most ideal requirement of system users. What is needed for having that function is to reduce the load of respective signal lines for transmitting a data access signal. Japan Laid-Open Application No. 7-182892 (filed on Dec. 22, 1993) discloses a semiconductor memory device having a hierarchical row decoder coupled to a main wordline, which can repair a defect without an increase in the number of redundancy main wordlines and occupy a minimal circuit area. Japan Laid-Open Application No. 8-340089 (filed on Mar. 2, 1995) discloses a DRAM device which can achieve a high speed by lowering the resistance of metal interconnections. Japan Laid-Open Application No. 10-308091 (filed on Mar. 2, 1997) discloses a semiconductor memory device which can suppress increase in the power consumption and achieve a high speed and a smaller occupied area while keeping the advantages of a hierarchical wordline. Japan Laid-Open Application No. 10-320979 (filed on Apr. 14, 1998) discloses a semiconductor memory device which can enhance a transmission speed and improve an integration level by shortening interconnections. U.S. Pat. No. 5,764,585 (filed on Jun. 7, 1996) discloses a DRAM device having a plurality of main row decoders each being coupled to one main wordline, and a plurality of sub-row decoders each being coupled to the one main wordline and a plurality of sub-wordlines, which can enhance an access speed of the device by reducing the load of the main row decoders. These above prior art devices are oriented toward a high speed by improving a chip layout,
Referring now to
FIG. 1
, a conventional DRAM device includes a plurality of memory cell arrays
10
,
12
, and
14
having a plurality of memory cells, a main row decoder
16
, a plurality of main wordlines MWL
0
-MWL
63
, a predecoder
30
, an address program circuit
32
, a redundancy main wordline RMWL, sub-row decoders ah, and redundancy sub-row decoders i-p. Now, wordlines crossing over a plurality of memory cell arrays and their drivers are described in detail below. For reference, an external address used in the following discussion is XA
0
-XA
8
.
The main row decoder
16
activates one of 64 main wordlines MWL
0
-MWL
63
according to an external row address XA
3
-XA
8
. Each of the main wordlines MWL
0
-MWL
63
is connected to one side of the main row decoder
16
and is horizontally arranged over the memory cell arrays
10
,
12
, and
14
. Each of sub-row decoders a, c, e, and g is disposed between the memory cell arrays
12
and
14
, and is connected to a main wordline through a corresponding one of sub-wordlines SW
0
, SW
2
, SW
4
, and SW
6
crossing over the memory cell array
12
and
14
. Each of sub-row decoders b, d, f, and h is disposed between the memory cell arrays
10
and
12
, and is connected to a main wordline through a corresponding one of sub-wordlines SW
1
, SW
3
, SW
5
, and SW
7
crossing over the cell arrays
10
and
12
.
The predecoder
30
activates one of eight predecoding lines SWPD
0
-SWPD
7
according to an external row address XA
0
-XA
2
. Each of the predecoding lines SWPD
0
-SWPD
7
is horizontally arranged over the memory cell arrays
10
,
12
, and
14
and is vertically arranged therebetween, coupling each of corresponding sub-row decoders a-h to one side of the predecoder
30
. In other words, each of the predecoding lines SWPD
0
-SWPD
7
is coupled to 64 sub-row decoders.
The address program circuit
32
receives the same address XA
3
-XA
8
as an external address inputted to the main row decoder
16
during a repair operation, activating a redundancy main wordline RMWL. The redundancy main wordline RMWL is coupled to one side of the address program circuit
32
and is horizontally arranged over the memory cell arrays
12
-
14
. Each of redundancy sub-row decoders i, k, m, and l is disposed between the memory cell arrays
12
and
14
, and couples a corresponding one of redundancy sub-wordlines RSWL
0
, RSWL
2
, RSWL
4
, and RSWL
6
to the redundancy main wordline RMWL. Each of redundancy row decoders j, l, n, and p is disposed between the memory cell arrays
10
and
11
, and couples a corresponding one of redundancy sub-wordlines RSWL
1
, RSWL
3
, RSWL
5
, and RSWL
7
to the redundancy main wordline RMWL.
The operations of the above semiconductor memory device are now described in detail. Each of the main wordlines MWL
0
-MWL
63
is activated according to the combination of external row addresses XA
3
-XA
8
. For example, when all external row addresses XA
3
-XA
8
inputted to the main row decoder
16
are ‘0’ (i.e., ‘000000’), only the main wordline MWL
0
is activated and the others, MWL
1
-MWL
63
, are inactive.
The predecoder
30
activates one of eight predecoding lines SWPD
0
-SWPD
7
according to an external row address XA
0
-XA
2
. For example, when all row addresses XA
0
-XA
2
are ‘0’ (i.e., ‘000’), the predecoding line SWPD
0
is activated and the other predecoding lines SWPD
1
-SWPD
7
are inactive.
As previously described, each of the sub-row decoders a-h is coupled to one of the main wordlines MWL
0
-MWL
63
through a corresponding sub-wordline. Therefore, each of the sub-row decoders a-h is activated when both a main wordline and a predecoding line, which are organically coupled to each other, are activated. As described in the example above, when the 0th main wordline MWL
0
and the 0th predecoding line are activated, only the sub-row decoder “a” is activated. Therefore, the sub-row decoder “a” activates memory cells coupled to the sub-wordline SW
0
.
The most ideal case is that a predecoding signal on the predecoding line SWPD
0
is supplied to only the sub-row decoder “a” coupled to the activated 0th main wordline MWL
0
. As shown in
FIG. 1
, however, the predecoding signal is supplied to all the sub-row decoders “a” coupled to the 63 main wordlines MWL
1
-MWL
63
as well as the activated main wordline MWL
0
(i.e., the predecoding signal is supplied to all the 64 sub-row decoders “a”), which becomes a load of the predecoding line SWPD
0
. From the standpoint of a signal, the data access signal on the predecoding line is subjected to a considerable physical resistance when it is supplied to the final cell. Therefore, the data access speed of the conventional memory device is reduced.
A repair is needed when a defective cell is created by various causes during a wafer fabricating process. When an external address for accessing a defective cell is inputted, a redundancy circuit disables a wordline coupled to a defective cell and enables a redundancy wordline. The conventional memory device of
FIG. 1
carries out the repair with a main wordline unit. For example, when there are defective cells coupled to the sub-wordline SWL
1
among cells in the memory cell array
12
, operations of the memory device are described below.
As mentioned above, the sub-wordline SWL
1
is activated when the main wordline MWL
0
and the predecoding line SWPD
1
are activated, i.e., an external address is ‘001000000’. Therefore

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