Static information storage and retrieval – Read/write circuit – Bad bit
Patent
1980-11-12
1982-12-21
Moffitt, James W.
Static information storage and retrieval
Read/write circuit
Bad bit
G11C 700
Patent
active
043653197
ABSTRACT:
A semiconductor device, in which a redundancy memory cell array is incorporated with a main memory cell matrix. One memory cell array is selected by two kinds of decoders and drivers. When the redundancy memory cell array is selected by a decoder, the decoder disables one kind of the decoders and drivers directly and, as a result, the other kind of the decoders and drivers are also disabled.
REFERENCES:
patent: 3753244 (1973-08-01), Sumilas et al.
Fujitsu Limited
Moffitt James W.
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