Semiconductor memory control circuit

Details Semiconductor memory control circuit Semiconductor memory control circuit

1987-12-01

1989-05-02

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Data refresh

G11C 700

Patent

active

048274534

ABSTRACT:
A semiconductor memory control circuit separates an externally input operation activation signal from an operation activation signal which is transferred inside a memory, and activates the internal operation activation signal only for a predetermined period of time. This predetermined period is determined in accordance with the cycle time required to achieve refreshment of a memory cell after the external operation activation signal is activated. Thereafter, even if the external operation activation signal is in an activated state, the internal operation activation signal is inactivated. When the internal operation activation signal is in the activated state and the external operation activation signal is inactivated, the internal operation activation signal is inactivated, in accordance with activation of the external operation activation signal.

REFERENCES:
patent: 4334295 (1982-06-01), Nagami
Minato et al., "A 20ns 64K CMOS SRAM," IEEE International Solid-State Circuits Conference, ISSCC Digest, pp. 222-223, Feb. 23, 1984.

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