Static information storage and retrieval – Read/write circuit – Data refresh
Reexamination Certificate
2001-01-22
2002-09-17
Phan, Trong (Department: 2818)
Static information storage and retrieval
Read/write circuit
Data refresh
C365S145000
Reexamination Certificate
active
06452852
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The present invention relates to a semiconductor memory configuration having a memory cell field composed of a large number of memory cells. The memory cells are driven via word lines and bit lines. A refresh logic circuit for refreshing the memory content of the memory cells in the memory cell field is provided. The memory cells contain a capacitor and a transistor, which are connected in series between a terminal for a potential and a node point.
A memory configuration of this type is disclosed, for example, in the form of a ferroelectric memory configuration, by the publication by Hiroki Koike et al. Titled, “60 ns 1 Mb Nonvolatile Ferroelectric Memory with Non-Driven Cell Plate Line Write/Read Scheme”, IEEE International Solid State Circuits Conference, pages 368 and 369, 1996. In order to be able to provide ferroelectric memory configurations with a high density, it is necessary to provide a common electrode for the storage capacitors and to keep the electrode at a constant potential. The constant potential is in particular formed by the arithmetic mean of the two voltages that are used on a bit line to write information into a memory cell. This concept is generally known as the “VDD/2 concept”. The problem in the case of memory cells composed of one transistor and one ferroelectric capacitor (1T1C cells) and in the case of memory cells composed of two transistors and two ferroelectric capacitors (2T2C cells) is that when the VDD/2 concept is applied, leakage currents in the substrate, so-called sub-threshold currents, and leakage currents through the blocked pn junction are unavoidable. Furthermore, leakage currents through the capacitor dielectric occur, whose absolute values are mostly negligibly low and which preassume a voltage drop at the memory capacitor that is already considerable. The magnitude of the various leakage currents is subject to severe fluctuations as a result of production tolerances and the high temperature dependence of the leakage currents.
In order to limit this power demand, in the ferroelectric memory configuration according to Published, German Patent Application DE 198 30 568 A1, it is proposed that the bit line be subdivided into k segments, which form local bit lines, and that the local bit lines be connected to a global bit line via k switches.
Furthermore, corresponding refresh logic circuits are generally known in other semiconductor memory configurations, such as DRAMs or EPROMs, and likewise prevent stored information being lost. In the case of DRAMs, because of the leakage currents that occur, the contents of all the memory cells are read out at regular time intervals and written back again. In the case of EPROMs, a loss of information because of the impermissible shifting of the storage transistor threshold voltage can make continual refreshing of the memory contents necessary.
U.S. Pat. No. 5,278,796 describes a refresh control circuit for a DRAM, which supplies a temperature-dependent refresh cycle. A temperature sensor generates a temperature-dependent signal, which is compared in a comparator with a predefined reference voltage. The time period until the refresh cycle is next switched on is consequently controlled in a temperature-dependent manner.
U.S. Pat. No. 5,539,703 shows a DRAM having a refresh drive circuit. In order to match the refresh cycles to fluctuations in the manufacturing process, a capacitor within the oscillator controlling the refresh is designed to be comparable with one or more capacitors in the memory cells.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a semiconductor memory configuration with a refresh logic circuit, and a method of refreshing a memory content of the semiconductor memory configuration which overcomes the above-mentioned disadvantages of the prior art devices and methods of this general type, in which the implementation of the refresh cycles are performed as beneficially as possible with regard to the necessary energy demand.
With the foregoing and other objects in view there is provided, in accordance with the invention, a semiconductor memory configuration. The memory configuration contains a terminal for connecting to a potential and a memory cell field having a number of memory cells and a node point. The memory cells each have a capacitor and a transistor connected in series between the terminal for the potential and the node point. Word lines are connected to and drive the memory cells, and bit lines are connected to the memory cells. A control circuit having a further node, a comparison circuit with an output, at least one memory cell and a refresh logic circuit connected to and refreshing a memory content of the memory cells in the memory cell field, is provided. The at least one memory cell of the control circuit contains a capacitor and a transistor connected in series between the terminal for the potential and the further node. The further node of the control circuit is connected to the comparison circuit, and the output of the comparison circuit controls the refresh logic circuit to cause the memory cells in the memory cell field to be refreshed.
According to the invention, in the semiconductor memory configuration and in the method of refreshing the memory content of the semiconductor memory configuration, with the aid of a comparison circuit, a characteristic variable of at least one reference memory cell is compared with a reference value and, if required, a refresh logic circuit is activated. The refresh operation in the memory cell field of the memory configuration is therefore not started in each case at rigid time intervals predefined by an internal timer circuit but is carried out only when it is actually needed. The refresh cycle is in this case triggered on the basis of the electrical state of the memory cells. In particular, no energy is wasted for unnecessary refresh cycles, which is very important in the case of the particularly low energy consumption required for mobile applications.
Advantageously, the memory configuration has specific reference memory cells, whose characteristic variables are evaluated by the comparison circuit in order to be able to control the refresh operation as required. These separate reference memory cells can be connected up to the comparison circuit in a simple way. Alternatively, it is also possible that, for example, memory cells in the memory cell field which have been shown to be particularly bad in the storage function test, or those particularly affected by leakage currents, are defined as reference measurement cells and used when operating the semiconductor memory. During the production and selection of the reference memory cells, care must be taken that, in terms of process engineering and the environmental conditions which influence them, in particular the operating temperature, these should correspond as far as possible to the memory cells to be refreshed.
In accordance with an added feature of the invention, the at least one memory cell of the control circuit has a storage node, and the comparison circuit is a differential amplifier which compares a potential of the storage node of the at least one memory cell of the control circuit with a reference voltage.
In accordance with an additional feature of the invention, the at least one memory cell of the control circuit is one of a plurality of reference memory cells whose characteristic variables are evaluated by the comparison circuit. And the refresh logic circuit refreshes both the memory content of the memory cells in the memory cell field and a memory content of the reference memory cells.
In accordance with another feature of the invention, the reference memory cells of the control circuit and the memory cells of the memory cell field are ferroelectric memory cells.
In accordance with a further feature of the invention, an input capacitance of the comparison circuit is negligibly small compared to a capacitance of the reference memory cells.
With the foregoing and other objects in view
Böhm Thomas
Braun Georg
Hönigschmid Heinz
Röhr Thomas
Infineon - Technologies AG
Phan Trong
LandOfFree
Semiconductor memory configuration with a refresh logic... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor memory configuration with a refresh logic..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory configuration with a refresh logic... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2817656