Semiconductor memory, components and layout arrangements thereof

Details Semiconductor memory, components and layout arrangements thereof Semiconductor memory, components and layout arrangements thereof

1992-06-18

1994-05-10

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Data refresh

331 57, 331186, G11C 11403

Patent

active

053114760

ABSTRACT:
There is provided in connection with a semiconductor memory, such as of the pseudostatic RAM, a layout of the circuit components thereof including a method of testing the memory. There is provided an oscillation circuit which is capable of withstanding bumping of the power source voltage (varying) which effects stabilization regarding the operation of the circuits included therewith including a refresh timer circuit. There is also provided for testing a refresh timer circuit and a semiconductor memory which includes a refresh timer circuit. There is further provided for an output buffer which is capable of high speed operation with respect to memory data readout, a voltage generating circuit which is capable of stable operation and a fuse circuit, such as provided in connection with redundant circuitry in the memory and which is characterized as having a configuration of a fuse logic gate circuit employing complementary channel MOSFETs together with a fuse. With respect to the semiconductor memory, such as the pseudostatic RAM, the initial count of the refresh timer counter circuit of the refresh timer circuit can be set at an optional value by applying a signal to an address input terminal, and a test mode can be effected in which the refresh period can be set at an optional value by accordingly applying a test control signal to a predetermined external terminal. Therefore, the discharge current of the oscillation circuit capacitor associated with the refresh timer circuit becomes stabilized, noting the particular layout arrangement regarding the polycrystalline silicon layer forming the resistor of the oscillation circuit, and the fact that same parasitic capacitances are effectively connected between the polycrystalline silicon resistor and the supply voltage of the circuit and between the polycrystalline silicon resistor and the ground potential of the circuit thereby cancelling any variation of the output of the power source. Therefore, variation of the oscillation frequency of the oscillation circuit attributable to the bumping of the power source can be effectively suppressed.

REFERENCES:
patent: 4804929 (1989-02-01), Kato et al.
patent: 4811295 (1989-03-01), Shinoda
patent: 4853654 (1989-08-01), Sakurai
Hitachi IC Memory Data Book, Hitachi, Ltd., pp. 229-234.

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