Semiconductor memory circuit with control of bit line voltage ba

Details Semiconductor memory circuit with control of bit line voltage ba Semiconductor memory circuit with control of bit line voltage ba

1987-02-25

1988-12-20

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Differential sensing

365189, 365202, 365207, G11C 700, G11C 702

Patent

active

047929286

ABSTRACT:
A semiconductor memory circuit includes: a plurality of memory cell columns each comprising a plurality of memory cells connected to a bit line, at least a dummy cell connected to a bit line constituting a bit line pair with said bit line, a sense amplifier connected between said two bit lines, and at least a FET for balancing the voltages of said two bit lines; and a balance control circuit for detecting the termination of selection of a dummy word line which is provided for the control of the dummy cell and thereafter operating the FET.

REFERENCES:
patent: 3962686 (1976-06-01), Matsue et al.
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patent: 4342102 (1982-07-01), Puar
patent: 4363111 (1982-12-01), Heightley
patent: 4367540 (1983-01-01), Shimohigashi
patent: 4393475 (1983-07-01), Kitagawa et al.
patent: 4475178 (1984-10-01), Kinoshita
patent: 4504748 (1985-03-01), Oritani
patent: 4507759 (1985-05-01), Yasui et al.
patent: 4551820 (1985-11-01), Matsuura
patent: 4658377 (1987-04-01), McElroy

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