Semiconductor memory circuit with bit lines discharging means

Details Semiconductor memory circuit with bit lines discharging means Semiconductor memory circuit with bit lines discharging means

1999-05-19

2000-09-12

Nelms, David

Static information storage and retrieval

Read/write circuit

Accelerating charge or discharge

36523003, G11C 700

Patent

active

061187143

ABSTRACT:
A semiconductor memory circuit reduces a current consumed by sense amplifiers, prevents erroneous operation, and can operate at high speed. The semiconductor memory circuit has a plurality of memory blocks each comprising a decoder, a plurality of memory cells, a plurality of sense amplifiers for amplifying potential changes in bit lines, a data latch for latching outputs from the sense amplifiers, a plurality of nMOS transistors for discharging the bit lines, an NAND gate for generating a sense amplifier de-energizing signal RD, and a reference voltage generator. In response to a memory block selecting signal CS, the NAND gate generates the sense amplifier de-energizing signal RD, which is applied to energize the nMOS transistors to discharge the bit lines of a memory block which is not selected.

REFERENCES:
patent: 4634890 (1987-01-01), Lee
patent: 4692902 (1987-09-01), Tanaka et al.
patent: 5479374 (1995-12-01), Kobayashi et al.
patent: 5703820 (1997-12-01), Kohno

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