Semiconductor memory circuit with a control circuit rising cell

Details Semiconductor memory circuit with a control circuit rising cell Semiconductor memory circuit with a control circuit rising cell

1999-06-15

2000-09-05

Nelms, David

Static information storage and retrieval

Read/write circuit

Signals

36518909, 36518526, G11C 700

Patent

active

061152978

ABSTRACT:
A semiconductor memory circuit includes a memory cell subarray, a subarray driver and a cell drain potential generator. The memory cell subarray includes word lines, memory cell transistors and a cell drain line selection transistor. Each of the memory cell transistors has a gate connected to one of the word lines, a drain and a source. The cell drain line selection transistor has a first terminal connected to the drains of the memory cell transistors, a second terminal and a gate. The semiconductor memory circuit further has a subarray driver connected to the gate of the cell drain line selection transistor for applying a predetermined potential to the cell drain line selection transistor in response to a write control signal and an address signal, and a cell drain potential generator connected to the second terminal of the cell drain line selection transistor for providing a cell drain potential to the second terminal of the cell drain line selection transistor in response to the write control signal. The cell drain potential generator has a delay circuit for slowly rising the cell drain potential.

REFERENCES:
patent: 5602789 (1997-02-01), Endoh et al.
patent: 5796657 (1998-08-01), Lee et al.
patent: 5812440 (1998-09-01), Suminaga et al.
patent: 5821909 (1998-10-01), Yiu et al.
patent: 5862734 (1999-02-01), Tanaka et al.

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