Semiconductor memory circuit having shift redundancy circuits

Details Semiconductor memory circuit having shift redundancy circuits Semiconductor memory circuit having shift redundancy circuits

1998-09-28

2000-02-01

Nelms, David

Static information storage and retrieval

Read/write circuit

Bad bit

3652257, G11C 700

Patent

active

060210753

ABSTRACT:
A semiconductor memory circuit comprises a plurality of shift redundancy circuits each of which is connected to two of write/read circuits and a redundancy write/read circuit. Also, a plurality of fuse elements are connected to each other in series. One of the fuse elements is connected between one of the shift redundancy circuits and a power supply potential and the others are each connected between two of the shift redundancy circuits. A program circuit is connected to one of the fuse elements disposed at an end portion opposite to the fuse element connected to the power supply potential, and selectively outputs a power supply potential or a ground potential. A plurality of cut fuse detecting circuits are provided which individually detect whether the fuse elements are cut or not, and control each of the write/read circuits and the redundancy write/read circuit in an activated or a inactivated state.

REFERENCES:
patent: 5146429 (1992-09-01), Kawai et al.
patent: 5255217 (1993-10-01), Tan
patent: 5260902 (1993-11-01), Pilling et al.
patent: 5608685 (1997-03-01), Johnson et al.
A. Ohba et al., "A 7NS 1MB BiCMOS ECL SRAM with Program-Free Redundancy", pp. 1-2, IEEE No. SYMO 4 Jun. 7, 1990.

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