Static information storage and retrieval – Read/write circuit – Testing
Reexamination Certificate
2003-06-12
2004-05-11
Hoang, Huan (Department: 2818)
Static information storage and retrieval
Read/write circuit
Testing
C365S063000, C365S203000
Reexamination Certificate
active
06735133
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a burn-in test circuit for screening a chip having a potential defect leading to an initial defect, by applying a voltage higher than that in a normal operation mode to a memory cell in a semiconductor memory circuit, especially, a DRAM chip.
2. Description of the Prior Art
FIG. 4
shows a configuration of a conventional semiconductor memory circuit. The conventional semiconductor memory circuit includes a memory cell array having a plurality of memory cells MC arranged in a matrix. Bit line pair BL
1
and /BL
1
and bit line pair BL
2
and /BL
2
are provided in rows of the matrix, while a plurality of word lines WL are provided in columns of the matrix. The memory cells MC are disposed at points of intersection of the bit lines and the word line WL. Each of the memory cells MC is a DRAM memory cell including one transistor and one capacitor.
A sense amplifier circuit
2
including a plurality of sense amplifiers SA is provided at each of opposite sides of the memory cell array
1
. The sense amplifiers SA disposed at the right side of the memory cell array
1
are connected to the bit line pair BL
1
and /BL
1
so as to amplify a minute potential difference between the bit line pair BL
1
and /BL
1
, while the sense amplifiers SA disposed at the left side of the memory cell array
1
are connected to the bit line pair BL
2
and /BL
2
so as to amplify a minute potential difference between the bit line pair BL
2
and /BL
2
.
As described in, for example, Japanese Patent Laid-Open Publication No. 10-340598 (1998), the memory cell array
1
of the conventional semiconductor memory circuit in
FIG. 4
has a so-called quarter pitch cell arrangement in which the bit line pair BL
1
and /BL
1
and the bit line pair BL
2
and /BL
2
are combined with each other telescopically in a direction of the word lines WL such that a plurality of sets each having the bit lines BL
1
, BL
2
, /BL
1
and /BL
2
arranged sequentially are repeated.
A bit line equalizing circuit BLEQ and a bit line and sense amplifier interconnecting circuit BLI are provided between the sense amplifier circuit
2
and the memory cell array
1
. The bit line equalizing circuit BLEQ functions to set the bit line pair to an identical potential during standby. In
FIG. 4
, two potentials VBL
1
and VBL
2
are provided as described in, for example, Japanese Patent Laid-Open Publication No. 2001-243794 (2001).
In a normal operation mode, the potentials VBL
1
and VBL
2
are set to be equal to each other. Each sense amplifier circuit
2
is shared by a pair of the bit line and sense amplifier interconnecting circuits BLI provided on its both sides and this is referred to as a “shared sense amplifier configuration”. At the time of activation of the word lines WL, the bit line and sense amplifier interconnecting circuit BLI is used for isolating one of the opposite bit line pairs of the respective sense amplifier circuits
2
from the corresponding sense amplifier circuit
2
so as to reduce stray capacity of the bit lines.
In order to secure reliability of the memory cells, a burn-in test in which a chip having a potential defect leading to an initial defect is screened by applying a voltage higher than that in the normal operation mode to the memory cells is performed prior to the shipment. The chip found to be defective by the burn-in test is replaced by an accepted chip and is discarded as a defective product so as to be rejected before the shipment. Rate for detecting the potential defect by the burn-in test is referred to as “burn-in acceleration”. The burn-in acceleration depends on a voltage applied in the burn-in test. Naturally, as the burn-in voltage is higher, the burn-in acceleration is higher. Meanwhile, as the burn-in period is longer, detection of the potential defect progresses further. Therefore, in order to heighten the burn-in effect, it is desirable that the burn-in test is performed at as high a voltage as possible for as long a time as possible. However, if the burn-in period is long, productivity deteriorates, so that the burn-in test is economically performed at such a high voltage as not to bring about breakdown of a transistor or the like.
The bit line equalizing circuits BLEQ are employed for applying a voltage stress among the neighboring bit lines BL
1
, BL
2
, /BL
1
and /BL
2
in the memory cell array
1
in the quarter pitch cell arrangement of
FIG. 4
so as to perform the burn-in test. Namely, if the potentials VBL
1
and VBL
2
are, respectively, set to high level and low level by setting a signal of the bit line equalizing Circuits BLEQ to high level, the bit line pair BL
1
and /BL
1
are set to high level. On the other hand, since the bit line pair BL
2
and /BL
2
are set to low level, the voltage stress can be applied among the neighboring bit lines BL
1
, BL
2
, /BL
1
and /BL
2
.
On the contrary, if the potentials VBL
1
and VBL
2
are, respectively, set to low level and high level, the bit line pair BL
1
and /BL
1
are set to low level and the bit line pair BL
2
and /BL
2
are set to high level. Therefore, by setting to different values the potentials VBL
1
and VBL
2
equal to each other in the normal operation mode, the voltage stress can be applied among the neighboring bit lines BL
1
, BL
2
, /BL
1
and /BL
2
.
FIG. 5
shows a configuration of another known semiconductor memory circuit. As described in, for example, Japanese Patent Laid-Open Publication No. 10-340598 (1998) referred to above, the memory cell array
1
of
FIG. 5
has a so-called half pitch cell arrangement in which the bit line pair BL
1
and /BL
1
and the bit line pair BL
2
and /BL
2
are provided alternately in the direction of the word lines WL such that a plurality of sets each having the bit lines BL
1
, /BL
1
, BL
2
and /BL
2
arranged sequentially are repeated. A decision as to which one of the memory cell array
1
of the quarter pitch cell arrangement in FIG.
4
and the memory cell array
1
of the half pitch cell arrangement in
FIG. 5
should be selected is made based on various factors, mainly, feasibility of microfabrication of the memory cells and feasibility for optimizing current driving force of a transistor in the memory cell.
Also in the known semiconductor memory circuit of
FIG. 5
, a voltage stress can be applied among the neighboring bit lines by using the bit line equalizing circuits BLEQ in the same manner as the conventional semiconductor memory circuit of FIG.
4
. Namely, if the potentials VBL
1
and VBL
2
are, respectively, set to high level and low level by setting a signal of the bit line equalizing circuits BLEQ to high level, the bit line pair BL
1
and /BL
1
are set to high level and the bit line pair BL
2
and /BL
2
are set to low level. Therefore, the voltage stress can be applied between the bit lines /BL
1
and BL
2
and between the bit lines /BL
2
and BL
1
.
On the contrary, if the potentials VBL
1
and VBL
2
are, respectively, set to low level and high level, the bit line pair BL
1
and /BL
1
are set to low level and the bit line pair BL
2
and /BL
2
are set to high level. Therefore, the voltage stress can be applied between the bit lines /BL
1
and BL
2
and between the bit lines /BL
2
and BL
1
. In the example shown in
FIG. 5
, the voltage stress cannot be applied between the neighboring bit lines BL
1
and /BL
1
and between the neighboring bit lines BL
2
and /BL
2
. Hence, also in the memory cell array
1
of the half pitch cell arrangement in
FIG. 5
, it is necessary to apply the voltage stress between the neighboring bit lines BL
1
and /BL
1
and between the neighboring bit lines BL
2
and /BL
2
. To this end, the sense amplifier SA should be activated at a potential corresponding to the voltage stress to be applied.
FIG. 6
is a circuit diagram of the sense amplifier SA. By setting sense amplifier activating signals SAP and SAN to low level and high level, respectively, the bit line pair BL and /BL are, respectively, set to high level and low level or low leve
Hoang Huan
McDermott & Will & Emery
Renesas Technology Corp.
LandOfFree
Semiconductor memory circuit having normal operation mode... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor memory circuit having normal operation mode..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory circuit having normal operation mode... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3233029