Semiconductor memory circuit having lower voltage supply for dat

Static information storage and retrieval – Read/write circuit – For complementary information

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327 51, 327543, G11C 700

Patent

active

053922433

ABSTRACT:
A read circuit is comprised of a circuit for reading out a data signal from one selected among a plurality of arrayed semiconductor memory cells by using a cascode type sense amplifier, in which the drop of the power supply voltage level and the level shift of the bit lines are properly set to allow the cascode type sense amplifier to operate at a low voltage. The bit lines are clamped to a low voltage level obtained by lowering the power supply voltage level and then the voltage level of the bit lines is shifted by one-stage wired-OR logic circuit in order to assure the stable operation of the cascode type sense amplifier.

REFERENCES:
patent: 4195356 (1980-03-01), O'Connell et al.
patent: 5199000 (1993-03-01), Takahashi
Takada et al., "A 5ns 1 Mb ECL BiCMOS SRAM", ISSCC Digest of Technical Papers, pp. 138-139, (1990). Feb. 15, 1990.

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