Semiconductor memory circuit having dummy cells connected to twi

Details Semiconductor memory circuit having dummy cells connected to twi Semiconductor memory circuit having dummy cells connected to twi

1989-07-26

1991-03-19

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Differential sensing

365207, G11C 1140

Patent

active

050016695

ABSTRACT:
A semiconductor memory circuit includes a plurality of bit line pairs each having intersecting portions where the paired bit lines intersect each other, and a plurality of pairs of memory word lines intersecting the bit lines in a direction substantially perpendicular to the bit lines. A plurality of memory cells are individually connected to the memory word lines and bit lines at intersections of one of the memory word lines of the individual memory word line pairs and one of the bit lines of the individual bit line pairs and at intersections of the other of the paired memory word lines and the other of the paired bit lines for storing charges each being associated with data to be sorted. A pair of dummy word lines are interposed between the intersecting portions of the bit lines and intersect the bit line pairs in a direction substantially perpendicular to the bit line pairs. A plurality of dummy cells are individually connected between the dummy word line pairs and the bit line pairs at intersections of one of the dummy word lines of the individual word line pairs and one of the bit lines of the individual bit line pairs and at intersections of the other of the paired dummy word lines and the other of the paired bit lines.

REFERENCES:
Tsutomu Yoshihara et al., "A Twisted Bit Line Technique for Multi-Mb DRAMs", 1988 IEEE International Solid-State Circuit Conference, Yoshihara et al., Feb. 19, 1988, pp. 238, 239.

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